Aspects of the present invention relate generally to field of circuit design and test and more specifically to using an adaptive square mesh for parasitic extraction during the verification and simulation of a circuit design.
Integrated circuit (IC) design is increasingly complex, sometimes involving millions of elements, shapes or geometries, and may be facilitated with an electronic design automation (EDA) tool that allows a designer to interactively position (“place”) and connect (“route”) various shapes on the circuit. The EDA tool then creates a circuit layout containing the physical locations and dimensions of the circuit's components, interconnections, and various layers from the original design that may then be fabricated, creating the IC. The designed IC is eventually fabricated by transferring or printing the circuit layout to a semiconductor substrate in a series of layers that collectively will form the features that constitute the devices that make up the components of the integrated circuit.
After or during the design and creation of an IC layout, validation, optimization, and verification operations are often performed on the IC layout using a set of testing, simulation, analysis and validation tools. These operations are conventionally performed in part to detect and correct placement, connectivity, and timing errors. For example, as part of the design and verification process, the IC design may undergo parasitic extraction. Parasitic extraction is a process that typically calculates the parasitic effects of the components and interconnects in a circuit design. The information related to the parasitic information (i.e. the parasitics) calculated and extracted from the design may aid in designing, characterizing, and optimizing the circuit design during the design and verification processes.
Conventional methods of parasitic extraction use a mesh to calculate interconnect parasitics. However, the conventional process of calculating parasitics often results in millions of parasitics extracted from a typical design. Additionally, conventional methods of parasitic extraction often use a uniform grid of rectangular shapes or a grid of calculated triangular shapes overlaid on the regions of the circuit design. For more accurate results, small polygons are used to form the mesh which results in even larger numbers of parasitic values extracted from the design. The extraction of so many parasitic values takes a significant amount of time and processing resources.
Accordingly, there is a need in the art to efficiently and accurately extract parasitic values from a circuit design.